1. Field of the Invention
The present invention relates to source synchronous data transfers, and more particularly, to a method and apparatus for optimizing source synchronous data transfers.
2. Discussion of the Related Art
Source synchronous data transfer schemes have been used to increase data transfer rates as compared to common clocked data transfer schemes. While common clocked data transfer schemes use a common clock signal for devices on the sending and receiving ends of a data transfer, in source synchronous data transfer schemes, the sending device provides one or more strobe signals with the data being transferred. The receiving device uses the strobe signal to sample the incoming data.
In order to maximize data transfer, the sampling point as determined by the strobe signal should be in the center of the data time period. This provides a setup margin of one-half data period and a hold margin of one-half data period. The strobe signal can be centered by the sending device or by the receiving device.
For example, Double Data Rate (DDR) memory devices use source synchronous transfers when data is read from the memory devices. Referring to FIG. 2A, a single ended data strobe signal (DQS) 110 is sent along with the data (DQ) 120 to be clocked to a memory controller. The DQS signal 110 is edge-aligned with the DQ signal 120 for read cycles and center-aligned with the DQ signal 120 for write cycles. The DQS signal 110 must be delayed relative to the DQ signal 120 to capture the data DQ 120 when it is valid and stable. For example, to capture the data 120 using the DQS signal 110 in a flip-flop, the DQS signal 120 needs to be delayed (delayed DQS 130) relative to the data 120 to satisfy the data set-up and hold time requirement of the flip-flop.
Referring to FIG. 6, ideally, DQ data signals should be detected by the memory controller at a time t1 during the data cycle with the period T. Time t1 corresponds to the center of the data cycle and it provides maximum timing margin, ½T, for data detection between data transition periods. When the DQS transition occurs in the center of the data cycle, the ideal optimal delay value has been found. FIG. 6 illustrates this ideal relationship between the data signal and the clock strobe signal.
A DQ data signal 120 transmitted so that it aligns ideally with respect to a delayed DQS signal 130 may arrive at the receiving device early or late with respect to the delayed DQS signal 130. In some circumstances, the best DQ data receive time may be at a point within the data cycle, other than the center, due to mismatches between the DQ and DQS paths.
Furthermore, the best delay for each DQS to provide the most capture margin is not necessarily in the center of the data cycle due to memory controller receiver circuit and board skew effects. Board topology may give rise to an undesired timing skew between the DQS signal and DQ data signals as they propagate from the DDR SDRAM to the memory controller.
Additionally, corruption of data transmitted via the Bus results not only from static characteristics, but also from data dependent phenomenon such as residual and cross-coupled signals. Residual signals on the Bus result from past transmissions on the same channel, and tend to reduce voltage and timing margins on the channel from one sampling interval to the next. Cross-coupled signals result from inductive coupling of signals on neighboring channels, rather than from past signals on the same channel. Cross-coupled signals also tend to reduce voltage and timing margins on the channel from one sampling interval to the next. Voltage margin as used herein refers to the signal integrity of the DQ and DQS signals in meeting requirements of a electrical bus specification such as the JEDEC SSTL—1.8 for DDR II.
FIG. 7A is a block diagram illustrating a prior art receiver 10. Input receiver 110 has a reference potential input terminal receiving a signal VREF 105 serving as a reference for determining whether an input signal is a high level signal or a low level signal. A typical receiver uses a comparator with a VREF signal configured midway between a high input voltage (VIH) and a low input voltage (VIL). The VREF signal is a high impedance DC voltage reference which tracks loosely with power supplies over time, but cannot respond to instantaneous noise. Conventionally, High Output Voltage (VOH) and Low Output Voltage (VOL) denote signals emerging from the transmitting source, and VIL and VIH denote signals arriving at the input of the receiving device, although they can be considered the same signal.
A VREF signal 105 is coupled to each internal receiver 110. VREF is typically generated from the device power supply (not shown) using a voltage divider resistor network. FIG. 7B is a timing diagram 125 illustrating an example signal relative to a high reference voltage (VREFh) and a low reference voltage (VREFl). The VREFh and VREFl values typically depend on power supply variation used to generate the VREF signal. The large voltage swing, i.e., the difference between a high voltage signal (VIH) and a low voltage signal (VIL), and stable signal levels above and below the VREF signal are required for reliable detection of signal polarity. The voltage swing of current single-ended signaling technologies is conventionally around 0.8 v.